Re: How it works - the electrical functionality of SI Prog (the serial HW interface for PonyProg)
Date: June 03, 2015 09:06PM
I will try to explain it more detailed. As an example device I will use spi eeprom 25LC640 with clock frequency 100kHz (=10us period). I have attached picture showing the time diagram of "read sequence" with highlighted important time events. On it we can see 4 "rows" of input/output lines namely CS (Chip Select), SCK (Serial Clock), SI (Serial Input) and SO (Serial Output). The red lines on the picture's left side are the rising edges of SCK and at this time is in place the "reading" of logical level at pin SI. The green lines show us the time when we must set the logical level for the next bit. The blue lines on the picture's right side are the falling edges of SCK and at this time is in place eeprom internal data reading. The green lines on the right side show us the time at which we can read data at pin SO. It is very important to keep logical levels and time sequence according to the device datasheet. I suggest to you to read the datasheet if you want even more detailed information.
After powering up of the serial device we must put CS line from logical 1 to logical 0. Setting logical 0 on Tx line causes rising voltage to level between +3V and +15V. The NPN transistor Q1 (located on the SI Prog base board) is now opened and CS line is at logical 0. This changes device status from standby mode to normal operation. Then we must prepare input data for serial device to pin SI. The read instruction has the length of one byte (8 bits). Each bit from this instruction (00000011) represents logical level and must be present on pin SI before rising edge of SCK. So the first bit (bit 7) of read instruction is 0, therefore we must set DTR line on PC's serial port to logical 0 and this must be set in 1/4 of SCK time period (2.5us) before the logical level on pin SCK goes high (for the very first bit at SI pin we must wait approximately 1/4 of SCK time period before we set SCK line high). Then we must set RTS line to logical 1 (SCK pin) and start the measuring of the time from the first rising edge of SCK after CS line is at logical 0 ( I will take name "time zero" ). The logical state at SCK and SI must not change within 1/2 of SCK time period (5us) to ensure the correct operation. Next we must set RTS line to logical 0 exactly in 1/2 of SCK time period (5us) after "time zero". After 3/4 of SCK time period (7.5us) we must set the logical level for the next bit at pin SI. 1 SCK time period (10us) after "time zero" we must set RTS line to logical 1 and so on until we "send" all 24 bits (8 bits for instruction and 16 bits for memory address at which we want to read data from eeprom). The clock must continually run until we get at least 1 byte (8 bits) of data at pin SO (CTS line on PC's serial port), else the read operation will fail. In time 23 and 3/4 of CK time period (237.5us) after "time zero" we can read logical level at pin SO for the first bit (bit 7) read from eeprom. Data will be present at pin SO always in time 24 (..25 till 31) and 3/4 of SCK after "time zero". After the last bit (bit 0) of byte was read, we can put CS line from logical 0 to logical 1 so the read sequence is terminated and eeprom is in standby mode.
Precise timing is very important to ensure the correct communication with serial device which you are connected to.
This is a very, very, very simplified example, but it explains how it works.
Edited 1 time(s). Last edit at 06/03/2015 09:10PM by sonix.
Serial_eeprom_25LC640_read_sequence_timing_highlight.png (98.5 KB)